Deskripsi Pekerjaan
ASTRAWAVE TECHNOLOGY is a dynamic and rapidly growing semiconductor company at the forefront of innovation, specializing in high-performance ASICs for Data Processing, IP Licensing, Network Switching, and Chiplet Interconnect. We are currently seeking passionate and skilled Analog Mixed-Signal (AMS) Layout Engineers at all experience levelsāfrom Junior to Seniorāto join our expanding team. This exciting opportunity is based in the heart of Singapore's business district at Raffles Place, Central Region.
In this critical role, you will be responsible for the physical implementation of complex analog and mixed-signal circuits. Collaborating closely with our international circuit design teams, you will drive floorplanning, layout, and physical verification to achieve optimal performance, power, and area (PPA) targets on advanced CMOS technology nodes. Your expertise will be crucial in bringing next-generation silicon solutions to life, impacting products that power the world's most demanding data centers and network infrastructures. From high-speed SerDes and PLLs to precision data converters, your layout skills will directly shape the success of our cutting-edge chiplet and interconnect technologies.
We foster a culture of technical excellence, continuous learning, and collaboration. At ASTRAWAVE, you will work alongside industry veterans, utilize state-of-the-art EDA tools (Cadence Virtuoso, Mentor Calibre), and contribute to real tape-outs from concept to mass production. Whether you are a seasoned professional looking to lead complex blocks or a junior engineer eager to accelerate your growth on advanced nodes, this role offers a unique platform to make a tangible impact in the rapidly evolving semiconductor landscape. Join us and be part of the team redefining how the world processes and moves data.
Tanggung Jawab
- Perform full-custom analog and mixed-signal layout design for advanced CMOS technology nodes (28nm and below).
- Collaborate with circuit design engineers to develop optimized floorplans and implement complex analog blocks (PLLs, ADCs, DACs, SerDes, I/Os).
- Execute detailed physical verification checks including DRC, LVS, ERC, and Antenna rule checking using industry-standard tools (Calibre, Assura).
- Participate in chip-level integration, top-level routing, and tape-out activities.
- Contribute to design rule documentation and layout methodology improvement.
- Mentor junior layout engineers and review their work to ensure quality and adherence to best practices.
- Drive parasitic extraction and EM/IR analysis to ensure post-layout performance meets specifications.
- Provide accurate project schedule estimates and status updates to project management.
Kualifikasi
- Diploma or Bachelor's/Master's Degree in Electrical Engineering, Electronics Engineering, or a related field.
- Proven experience in analog/mixed-signal custom layout design. Junior: 1-3 years. Mid/Senior: 4+ years.
- Strong proficiency with Cadence Virtuoso Layout Suite (XL/GXL) and physical verification tools (Mentor Calibre).
- Solid understanding of semiconductor physics, CMOS process flows, and layout-dependent effects (LDE).
- Experience with high-speed, low-power, and matching-sensitive layout techniques.
- Proficiency in scripting languages (Skill, Perl, Python) is a plus.
- Excellent problem-solving abilities and meticulous attention to detail.
- Outstanding communication and teamwork skills, comfortable working in a fast-paced environment.