Deskripsi Pekerjaan
Lattice Semiconductor is a global leader in programmable logic solutions, dedicated to providing innovative, low-cost, and low-power design technologies. We are currently seeking a skilled Design Verification (DV) Engineer to join our dynamic engineering team. In this pivotal role, you will be responsible for ensuring the quality, functionality, and performance of our next-generation FPGA and CPLD products. You will work closely with design and architecture teams to develop rigorous verification plans, implement comprehensive testbenches, and drive the verification closure of complex digital designs.
As a DV Engineer at Lattice, you will leverage your expertise in verification methodologies to simulate, debug, and validate RTL code. You will play a critical role in our chip development lifecycle, identifying potential design flaws early and ensuring our products meet the highest industry standards. If you are passionate about verification and want to work with cutting-edge technology in a collaborative environment, we encourage you to apply.
Tanggung Jawab
- Develop and execute comprehensive verification plans and test cases for complex digital designs.
- Design and implement SystemVerilog and UVM-based testbenches for stimulus generation and functional coverage.
- Analyze simulation results and debug complex functional failures to ensure design integrity.
- Collaborate with cross-functional teams including architects, designers, and product managers.
- Drive verification closure and meet coverage goals throughout the development cycle.
- Maintain and update verification environments to support regression testing and new feature integration.
- Perform code reviews and provide feedback to improve overall verification quality.
Kualifikasi
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- Strong understanding of digital logic design fundamentals and computer architecture.
- Proficiency in SystemVerilog, Verilog, and VHDL with a focus on verification constructs.
- Experience with the Universal Verification Methodology (UVM) is highly preferred.
- Familiarity with EDA tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
- Knowledge of code coverage, functional coverage, and assertion-based verification (SVA).
- Excellent problem-solving skills and the ability to work in a fast-paced, collaborative team environment.