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Engineering 🏢 Full Time ⭐️ Terverifikasi

Digital IC Design Engineer (RTL/Verilog/Logic Synthesis/DFT)

Trust Recruit
East Region
Estimasi Gaji
SGD 7.000 – SGD 8.500
Live Update
3 Mei 2026
Batas Akhir
3 Mei 2027

Deskripsi Pekerjaan

Are you passionate about shaping the future of semiconductor technology? Join our team as a Digital IC Design Engineer and be at the forefront of cutting-edge chip development. We are seeking a talented professional to design, develop, and optimize complex digital integrated circuits that power the next generation of electronic devices.

In this role, you will collaborate with cross-functional teams to translate system requirements into efficient hardware implementations. You'll tackle challenging problems in logic optimization, timing closure, and testability while ensuring our designs meet the highest standards of quality and performance.

The position offers exciting opportunities to work on advanced projects involving RTL design, logic synthesis, and design-for-test methodologies. You'll leverage industry-leading EDA tools and contribute to developing innovative solutions that push the boundaries of what's possible in digital design.

We value candidates who thrive in dynamic environments and are committed to continuous learning. If you're ready to make an impact in a rapidly evolving field and grow your expertise alongside industry professionals, we want to hear from you.

Tanggung Jawab

  • Design and develop complex digital ICs using RTL design methodologies (Verilog/SystemVerilog)
  • Perform logic synthesis, timing analysis, and optimization to meet performance targets
  • Implement design-for-test (DFT) strategies including scan insertion and ATPG
  • Collaborate with verification teams to ensure robust design quality and coverage
  • Debug and resolve timing violations, synthesis issues, and design convergences
  • Develop and maintain design scripts for automation and flow improvement
  • Interface with backend teams for place-and-route and physical verification
  • Document design specifications and provide technical guidance to junior engineers

Kualifikasi

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
  • Minimum 3-5 years of experience in digital IC design with RTL/Verilog
  • Proficiency in logic synthesis, timing closure, and DFT techniques
  • Experience with industry-standard EDA tools (Synopsys, Cadence, or Mentor)
  • Strong understanding of semiconductor process technologies and constraints
  • Experience with ASIC or SoC design flows from specification to tapeout
  • Programming skills in Perl, Python, or TCL for design automation
  • Excellent problem-solving abilities and communication skills

Keahlian yang Dibutuhkan

RTL Design Verilog SystemVerilog Logic Synthesis DFT ASIC Design SoC Timing Analysis EDA Tools Perl Python TCL Scan Insertion ATPG Semiconductor IC Design VLSI

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