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Engineering 🏢 Full Time ⭐️ Terverifikasi

Layout Engineer

Key ASIC Berhad
Bandar Utama, Selangor
Estimasi Gaji
RM 4.500 – RM 5.500
Live Update
9 Juli 2026
Batas Akhir
9 Jul 2027

Deskripsi Pekerjaan

Are you ready to shape the future of cutting-edge IC design? Key ASIC Berhad is seeking a highly skilled Layout Engineer to join our innovative technical team. We are dedicated to pushing the boundaries of semiconductor technology and are looking for a detail-oriented professional who thrives in a dynamic environment.

In this role, you will play a critical part in the physical implementation of integrated circuits. You will collaborate closely with design and verification teams to ensure that our chips meet the highest standards of performance, reliability, and manufacturability. Join us to experience a competitive salary, comprehensive benefits, and a clear trajectory for career growth in the fast-paced tech industry.

At Key ASIC Berhad, we value innovation and excellence. Our engineers work on challenging projects that have a real-world impact, utilizing state-of-the-art tools and methodologies. If you are passionate about VLSI and physical design, this is the perfect opportunity to advance your career with a forward-thinking organization.

Tanggung Jawab

  • Perform full-custom or semi-custom layout design for analog and mixed-signal integrated circuits.
  • Execute Design Rule Checks (DRC) and Layout Versus Schematic (LVS) verification using industry-standard EDA tools.
  • Collaborate with circuit designers to optimize layout for performance, power, and area (PPA).
  • Manage the entire tape-out process, including generating GDSII files and managing design libraries.
  • Implement Design for Manufacturability (DFM) guidelines to ensure high yield production.
  • Perform timing analysis and signal integrity checks to ensure signal quality.
  • Document all design activities and create detailed technical specifications.

Kualifikasi

  • Bachelor’s degree in Electrical Engineering, Electronics Engineering, or Microelectronics.
  • Minimum of 2-4 years of experience in IC layout design, preferably in the semiconductor or ASIC industry.
  • Strong knowledge of CMOS processes and semiconductor fabrication technology.
  • Proficiency in using EDA tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys PVS.
  • Familiarity with Python or Perl scripting for automation tasks is a plus.
  • Excellent attention to detail and problem-solving skills.
  • Ability to work effectively in a cross-functional team environment.

Keahlian yang Dibutuhkan

IC Layout Physical Design VLSI DRC LVS Cadence Virtuoso Mentor Graphics GDSII Semiconductor CMOS Analog Layout Mixed-Signal Design Tape-out PPA Optimization

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