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Engineering 🏢 Full Time ⭐️ Terverifikasi

Physical Design Engineer (Junior/ Senior/ Staff)

Talent Trader Group
Penang
Estimasi Gaji
MYR 60.000 – MYR 180.000
Live Update
17 Juni 2026
Batas Akhir
17 Jun 2027

Deskripsi Pekerjaan

Join Talent Trader Group as a Physical Design Engineer and shape the future of semiconductor innovation. We're seeking passionate professionals at Junior, Senior, or Staff levels to drive cutting-edge VLSI and ASIC implementations. You'll collaborate with cross-functional teams to transform logical designs into optimized physical layouts, ensuring performance, power efficiency, and manufacturability excellence. This role offers hands-on experience with industry-leading EDA tools and methodologies in a dynamic, growth-oriented environment.

Talent Trader Group empowers engineers to tackle complex challenges in high-performance computing, IoT, and communication technologies. You'll contribute to tape-ready designs while advancing your expertise in physical verification, timing closure, and power analysis. Our commitment to professional development ensures continuous learning through mentorship programs and exposure to emerging semiconductor technologies.

Tanggung Jawab

  • Perform physical design implementation including floorplanning, placement, clock tree synthesis, and routing
  • Optimize designs for timing, power, and area (PPA) using Synopsys IC Compiler and Cadence Innovus
  • Conduct comprehensive physical verification (DRC/LVS) and ECO iterations
  • Analyze and resolve timing violations, power integrity issues, and signal integrity constraints
  • Develop and maintain physical design methodologies and automation scripts
  • Collaborate with logic design and verification teams for seamless integration
  • Perform sign-off analysis for tape-out readiness and yield improvement

Kualifikasi

  • Bachelor's degree in Electrical/Computer Engineering or related field
  • 3-10+ years of physical design experience based on seniority level
  • Proficiency in Synopsys IC Compiler/Cadence Innovus and verification tools
  • Strong knowledge of CMOS process nodes (16nm/7nm/5nm) and design constraints
  • Expertise in scripting languages (Tcl/Perl/Python) for automation
  • Experience with low-power design techniques (UPF/CPF)
  • Excellent problem-solving skills and attention to detail
  • For Staff roles: Leadership experience and methodology development background

Keahlian yang Dibutuhkan

Physical Design VLSI ASIC Synopsys Cadence Place and Route Timing Analysis Power Analysis EDA tools Tcl Perl Python DRC/LVS Clock Tree Synthesis Low-Power Design

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