Deskripsi Pekerjaan
Team Introduction
The Silicon Platform Team acts as the core R&D middleware group for chip development within ByteDance. We are dedicated to building the foundational silicon infrastructure that powers our massive ecosystem. As a Physical Design Engineer, you will play a pivotal role in the physical implementation of our next-generation AI accelerators and high-performance computing platforms. Our team covers the full spectrum of the design flow, from architecture definition to silicon sign-off, ensuring that our chips meet the highest standards of performance, power, and area (PPA).
Role Overview
We are seeking a skilled and motivated Physical Design Engineer to join us in Singapore. In this role, you will collaborate closely with architecture, verification, and logic design teams to deliver robust and efficient silicon solutions. You will leverage your expertise in advanced EDA tools to optimize chip layouts, manage complex timing constraints, and drive the tape-out process for production-ready products.
Tanggung Jawab
- Lead the physical implementation of next-generation AI/ML chips, including floorplanning, placement, and routing.
- Perform timing closure analysis and optimization to ensure high-frequency performance and signal integrity.
- Conduct power analysis and optimization strategies to enhance energy efficiency for mobile and edge devices.
- Collaborate with the architecture team to define efficient floorplans and partitioning strategies.
- Perform Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification to ensure manufacturability.
- Mentor junior engineers and participate in technical reviews to drive engineering excellence.
- Participate in the full tape-out cycle, including sign-off and silicon bring-up support.
Kualifikasi
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- 3-5+ years of experience in Physical Design (PD) flows for ASIC/SoC development.
- Strong proficiency with industry-standard EDA tools such as Synopsys (ICC2, Innovus) or Cadence (Genus, Innovus, Virtuoso).
- Deep understanding of digital implementation methodologies, timing analysis, and power optimization.
- Experience with custom IC design or advanced packaging technologies is a plus.
- Excellent problem-solving skills and the ability to work effectively in a fast-paced, cross-functional team environment.
- Strong communication skills in English.