Deskripsi Pekerjaan
Realtek is seeking a highly skilled and motivated Senior/Staff/Principal Design Verification Engineer to join our dynamic team in Jurong East. In this pivotal role, you will be responsible for the verification of complex semiconductor designs, ensuring they meet rigorous quality and reliability standards before mass production. We are looking for a visionary engineer who can drive the verification methodology forward, optimize verification environments, and collaborate closely with design teams to deliver world-class SoC solutions.
As a key member of our verification team, you will leverage your deep technical expertise in SystemVerilog and UVM to build scalable and reusable verification IP. You will be instrumental in defining verification strategies, conducting functional coverage analysis, and closing complex design bugs. This position offers an excellent opportunity to work on cutting-edge technology with industry leaders, contributing to the next generation of high-performance computing and connectivity products.
Tanggung Jawab
- Develop comprehensive verification plans and strategies for complex digital ASIC and SoC designs.
- Design and implement verification environments using SystemVerilog, UVM, and constrained random stimulus generation.
- Create and maintain reusable verification components (agents, sequences, and utilities) to improve efficiency.
- Analyze functional, code, and assertion coverage to identify gaps and drive verification closure.
- Debug complex functional failures and collaborate with design engineers to resolve issues efficiently.
- Contribute to the continuous improvement of verification methodologies, tools, and flows.
- Participate in code reviews, design reviews, and technical discussions to ensure design integrity.
Kualifikasi
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Minimum of 5 years of experience in semiconductor design verification, with a strong preference for Senior/Principal level candidates.
- Strong proficiency in SystemVerilog, UVM, and verification methodologies.
- In-depth knowledge of digital design fundamentals, RTL coding, and timing analysis.
- Experience with formal verification techniques and debug tools (e.g., VCS, Questa, SpyGlass) is highly desirable.
- Excellent problem-solving skills, strong communication abilities, and the capacity to work effectively in a cross-functional team environment.