Deskripsi Pekerjaan
We are seeking a highly skilled Senior Hardware Engineer - Physical Layer to join an elite R&D team in Singapore's Central Region. This is a unique opportunity to architect and implement cutting-edge physical layer solutions for next-generation high-speed communication systems.
In this role, you will take ownership of the entire hardware development lifecycle for complex PHY layer designs. You will define system architecture, drive component selection, and lead design reviews for high-speed digital and mixed-signal circuits. Your deep expertise in Signal Integrity (SI), Power Integrity (PI), and electromagnetic simulation will be critical as you optimize channels for SerDes, PAM-4, and NRZ interfaces operating at 112Gbps and beyond. You will work on advanced challenges including jitter analysis, equalization techniques, and advanced packaging.
Collaboration is key to this role. You will partner closely with ASIC design, firmware, and systems engineering teams to ensure seamless integration of hardware platforms. The successful candidate will also mentor junior engineers, champion best practices in high-speed design, and drive continuous improvement in our hardware development processes. If you are a hands-on engineer who thrives on solving complex technical problems and wants to make a significant impact on world-class products, we want to hear from you.
Tanggung Jawab
- Lead the design, simulation, and validation of high-speed digital and mixed-signal circuits for PHY layer implementations (SerDes, PLLs, equalizers).
- Define hardware architecture, perform component selection, and complete schematic design for complex FPGA/ASIC-based systems.
- Conduct comprehensive Signal Integrity (SI) and Power Integrity (PI) analysis using industry-standard tools (HFSS, ADS, Sigrity).
- Oversee PCB layout guidance for high-speed designs, ensuring optimal routing, stack-up, and impedance control.
- Develop and execute detailed test plans for hardware bring-up, characterization, and compliance testing of PHY layer interfaces.
- Collaborate closely with cross-functional teams (Firmware, ASIC, Systems) to integrate and debug physical layer control loops and algorithms.
- Drive root cause analysis for complex hardware issues, implementing robust corrective and preventive actions.
- Document design specifications and test reports, and provide technical mentorship to junior engineers.
Kualifikasi
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Electronics Engineering, or a closely related field.
- Minimum 5+ years of hands-on experience in high-speed hardware design with a strong focus on Physical Layer technologies.
- Deep understanding of PHY architectures (PAM-4, NRZ), SerDes design principles, clocking, and equalization techniques (CTLE, DFE, FFE).
- Proficiency in schematic capture (Cadence OrCAD/Allegro) and familiarity with high-speed PCB layout guidelines.
- Extensive experience with SI/PI simulation tools (Ansys HFSS, Cadence Sigrity, Keysight ADS).
- Hands-on experience with high-speed lab equipment: Real-Time Oscilloscopes (>50 GHz), BERTs, VNAs, and TDRs.
- Familiarity with industry standards such as IEEE 802.3ck, OIF-CEI, or PCI Express Gen 5/6.
- Excellent problem-solving skills and a proven ability to drive technical projects from concept to completion.